Physical Design Engineer

Experience: 8 + Years

• Hands-on Experience Block Level P&R / Sub-system Level P&R/ Tile Level P&R.
• Process node experience to be in the range of 28nm & below (i.e. 28 nm, 16 nm, 10 nm, 7 nm). 
• Responsible for full-chip implementation of complex SoCs (RTL-to-GDSII)